Tutorials

Design of CMOS Inverter and Basic Gates

Ritam Dutta
28 Jan 2017
Read Time : 30 Minutes
Design of CMOS Inverter and Basic Gates

Design of CMOS Inverter (NOT) Gate

A CMOS Inverter is the simplest logic that uses one nMOS and one pMOS transistor. The nMOS is used in Pull Down Network (PDN) and the pMOS is used in Pull Up Network (PUN).
Operation: When input is low, the nMOS is OFF and the pMOS is ON. Hence, the output is connected to VDD through pMOS. When the input is high, the nMOS is ON and the pMOS is OFF. Hence the output is connected to ground through nMOS.

Now for more number of transistor design using CMOS VLSI Design, there are two rules to be followed:

a)    If AND operation (multiplication) is to be designed, then nMOS transistor(s) need to be connected in SERIES at PDN and pMOS transistor(s) in PARALLEL at PUN.
b)   If OR operation (addition) is to be designed, then nMOS transistor(s) need to be connected in PARALLEL at PDN and pMOS transistor(s) in SERIES at PUN.

Design of 2 input CMOS NAND Gate

To design such basic logic gates the steps need to be followed:

Step 1:    Write the Boolean expression of the given function.
Step 2:    Take the complement of the output. As CMOS always perform automatic inversion.
Step 3:    For more than one number of MOS transistor, follow the design rules said above (a) & (b).
Step 4:    Design the target object (i. e; CMOS NAND)
Step 5:    Draw the Truth Table of the logic gate.
Step 6:   Perform each combinations by providing logic HIGH (1) or logic LOW (0) values at the corresponding input(s) and check the desired output.

Watch the youtube video for proper understanding.

Follow us on Facebook_Page, Youtube_Channel and Join us on Facebook_Group

Authored By Ritam Dutta

Ritam Dutta is an official partner of "Day On My Plate". He is an entrepreneur in mind and passionate blogger by heart. Moreover, he is also an academician, author, public speaker, investor, and internet personality.

 

Basics Time Complexity Analysis Motivation of Design and Analysis of Algorithm To study the PN junction diode characteristics under Forward bias conditions To study the input and output characteristics of a BJT in Common Emitter configuration