**Design of 2 input CMOS Half Adder Circuit**

A CMOS Half Adder circuit is the logic that uses more than one nMOS and one pMOS transistor(s). The nMOS(s) is used in Pull Down Network (PDN) and the pMOS(s) is used in Pull Up Network (PUN).

**Operation: **When input is low, the nMOS is OFF and the pMOS is ON. Hence, the output is connected to VDD through pMOS. When the input is high, the nMOS is ON and the pMOS is OFF. Hence the output is connected to ground through nMOS.

Now for more number of transistor design using CMOS VLSI Design, there are two rules to be followed:

**a)** If AND operation (multiplication) is to be designed, then nMOS transistor(s) need to be connected in SERIES at PDN and pMOS transistor(s) in PARALLEL at PUN.

**b)** If OR operation (addition) is to be designed, then nMOS transistor(s) need to be connected in PARALLEL at PDN and pMOS transistor(s) in SERIES at PUN.

**Design of 2 input CMOS Half Adder (HA) Circuit**

To design such basic logic gates the steps need to be followed:

**Step 1:** Write the Boolean expression of the given function.

**Step2:** Take the complement of the output. As CMOS always perform automatic inversion.

**Step 3:** For more than one number of MOS transistor, follow the design rules said above (a) & (b).

**Step 4:** Design the target object (i. e; CMOS HA)

**Step 5:** Draw the Truth Table of the logic gate.

**Step 6:** Perform each combinations by providing logic HIGH (1) or logic LOW (0) values at the corresponding input(s) and check the desired output.

Here in Half Adder circuit as there are 2 output(s), like: SUM and CARRY. So the SUM and CARRY can be designed separately or together also.

SUM performs XOR operation and CARRY performs AND operation.

The detail of working of 2 input CMOS HA is available in Youtube Channel.

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